5-1 march 1997 hd-6402 cmos universal asynchronous receiver transmitter (uart) features ? 8.0mhz operating frequency (hd-6402b) ? 2.0mhz operating frequency (hd-6402r) ? low power cmos design ? programmable word length, stop bits and parity ? automatic data formatting and status generation ? compatible with industry standard uarts ? single +5v power supply ? cmos/ttl compatible inputs description the hd-6402 is a cmos uart for interfacing computers or microprocessors to an asynchronous serial data channel. the receiver converts serial start, data, parity and stop bits. the transmitter converts parallel data into serial form and automatically adds start, parity and stop bits. the data word length can be 5, 6, 7 or 8 bits. parity may be odd or even. parity checking and generation can be inhibited. the stop bits may be one or two or one and one-half when transmit- ting 5-bit code. the hd-6402 can be used in a wide range of applications including modems, printers, peripherals and remote data acquisition systems. utilizing the intersil advanced scaled saji iv cmos process permits operation clock frequencies up to 8.0mhz (500k baud). power requirements, by compar- ison, are reduced from 300mw to 10mw. status logic increases ?exibility and simpli?es the user interface. pinout hd-6402 (pdip, cerdip) top view ordering information package temperature range 2mhz = 125k baud 8mhz = 500k baud pkg. no. plastic dip -40 o c to +85 o c hd3-6402r-9 hd3-6402b-9 e40.6 cerdip -40 o c to +85 o c hd1-6402r-9 hd1-6402b-9 f40.6 smd# -55 o c to +125 o c 5962-9052501mqa 5962-9052502MQA f40.6 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 v cc nc gnd rrd rbr8 rbr7 rbr6 rbr5 rbr4 rbr3 rbr2 rbr1 pe fe oe sfd rrc drr dr rri 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 trc epe cls1 cls2 sbs pi crl tbr8 tbr7 tbr6 tbr5 tbr4 tbr3 tbr2 tbr1 tro tre tbrl tbre mr file number 2956.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999
5-2 functional diagram control de?nition control word character format cls 2 cls 1 pi epe sbs start bit data bits parity bit stop bits 0 0 0 0 0 1 5 odd 1 0 0 0 0 1 1 5 odd 1.5 0 0 0 1 0 1 5 even 1 0 0 0 1 1 1 5 even 1.5 0 0 1 x 0 1 5 none 1 0 0 1 x 1 1 5 none 1.5 0 1 0 0 0 1 6 odd 1 0 1 0 0 1 1 6 odd 2 0 1 0 1 0 1 6 even 1 0 1 0 1 1 1 6 even 2 0 1 1 x 0 1 6 none 1 0 1 1 x 1 1 6 none 2 1 0 0 0 0 1 7 odd 1 1 0 0 0 1 1 7 odd 2 1 0 0 1 0 1 7 even 1 1 0 0 1 1 1 7 even 2 1 0 1 x 0 1 7 none 1 1 0 1 x 1 1 7 none 2 1 1 0 0 0 1 8 odd 1 1 1 0 0 1 1 8 odd 2 1 1 0 1 0 1 8 even 1 1 1 0 1 1 1 8 even 2 1 1 1 x 0 1 8 none 1 1 1 1 x 1 1 8 none 2 (24) tre (22) tbre ? (23) tbrl (40) trc (38) cls1 (37) cls2 (34) crl (21) mr (17) rrc (18) drr (19) dr ? (16) sfd ? oe ? fe ? pe (15) (14) (13) (5) (6) (7) ? rbr8 3-state buffers (8) (9) (10) (11) (12) ? rbr1 receiver buffer register receiver register multiplexer multiplexer transmitter register transmitter buffer register start stop parity logic parity logic start logic stop logic control register receiver timing and control transmitter timing and control ? these outputs are three-state (4) rrd (20) rri (35) pi (39) epe (16) sfd (36) sbs (25) tro (26) tbr1 (27) (30) (29) (28) (31) (32) (33) tbr8 hd-6402
5-3 pin description pin type symbol description 1v cc ? positive voltage supply 2 nc no connection 3 gnd ground 4 i rrd a high level on receiver register disable forces the receiver holding out-puts rbr1-rbr8 to high impedance state. 5 o rbr8 the contents of the receiver buffer regis- ter appear on these three-state outputs. word for- mats less than 8 characters are right justi?ed to rbr1. 6 o rbr7 see pin 5-rbr8 7 o rbr6 see pin 5-rbr8 8 o rbr5 see pin 5-rbr8 9 o rbr4 see pin 5-rbr8 10 o rbr3 see pin 5-rbr8 11 o rbr2 see pin 5-rbr8 12 o rbr1 see pin 5-rbr8 13 o pe a high level on parity error indicates received parity does not match parity programmed by control bits. when parity is inhibited this output is low. 14 o fe a high level on framing error indicates the first stop bit was invalid. 15 o oe a high level on overrun error indicates the data received flag was not cleared before the last character was transferred to the receiver buffer register. 16 i sfd a high level on status flags disable forces the outputs pe, fe, oe, dr, tbre to a high im- pedance state. 17 i rrc the receiver register clock is 16x the receiver data rate. 18 i drr a low level on data received reset clears the data received output dr to a low level. 19 o dr a high level on data received indicates a character has been received and transferred to the receiver buffer register. 20 i rri serial data on receiver register input is clocked into the receiver register. 21 i mr a high level on master reset clears pe, fe, oe and dr to a low level and sets the transmitter register empty (tre) to a high level 18 clock cycles after mr falling edge. mr does not clear the receiv- er buffer register. this input must be pulsed at least once after power up. the hd-6402 must be master reset after power up. the reset pulse should meet v ih and t mr . wait 18 clock cycles after the falling edge of mr before beginning operation. 22 o tbre a high level on transmitter buffer regis- ter empty indicates the transmitter buffer register has transferred its data to the transmitter register and is ready for new data. 23 i tbrl a low level on transmitter buffer regis- ter load transfers data from inputs tbr1- tbr8 into the transmitter buffer register. a low to high transition on tbrl initiates data transfer to the transmitter register. if busy, transfer is auto- matically delayed so that the two characters are transmitted end to end. 24 o tre a high level on transmitter register emp- ty indicates completed transmission of a charac- ter including stop bits. 25 o tro character data, start data and stop bits appear se- rially at the transmitter register output. 26 i trb1 character data is loaded into the transmitter buffer register via inputs tbr1-tbr8. for character formats less than 8 bits the tbr8, 7 and 6 inputs are ignored corresponding to their pro- grammed word length. 27 i tbr2 see pin 26-tbr1. 28 i tbr3 see pin 26-tbr1. 29 i tbr4 see pin 26-tbr1. 30 i tbr5 see pin 26-tbr1. 31 i tbr6 see pin 26-tbr1. 32 i tbr7 see pin 26-tbr1. 33 i tbr8 see pin 26-tbr1. 34 i crl a high level on control register load loads the control register with the control word. the control word is latched on the falling edge of crl. crl may be tied high. 35 i pi a high level on parity inhibit inhibits parity gen- eration, parity checking and forces pe output low. 36 i sbs a high level on stop bit select selects 1.5 stop bits for 5 character format and 2 stop bits for other lengths. 37 i cls2 these inputs program the character length selected (cls1 low cls2 low 5 bits) (cls1 high cls2 low 6 bits) (cls1 low cls2 high 7 bits) (cls1 high cls2 high 8 bits.) 38 i cls1 see pin 37-cls2. 39 i epe when pi is low, a high level on even parity enable generates and checks even parity. a low level selects odd parity. 40 i trc the transmitter register clock is 16x the transmit data rate. ? a 0.1 m f decoupling capacitor from the v cc pin to the gnd is rec- ommended. pin type symbol description 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 hd-6402 hd-6402
5-4 transmitter operation the transmitter section accepts parallel data, formats the data and transmits the data in serial form on the transmitter regis- ter output (tro) terminal (see serial data format). data is loaded from the inputs tbr1-tbr8 into the transmitter buffer register by applying a logic low on the transmitter buffer register load ( tbrl) input (a). valid data must be present at least t set prior to and t hold following the rising edge of tbrl. if words less than 8 bits are used, only the least signi?cant bits are transmitted. the character is right justi?ed, so the least signi?cant bit corresponds to tbr1 (b). the rising edge of tbrl clears transmitter buffer register empty (tbre). 0 to 1 clock cycles later, data is transferred to the transmitter register, the transmitter register empty (tre) pin goes to a low state, tbre is set high and serial data information is transmitted. the output data is clocked by transmitter register clock (trc) at a clock rate 16 times the data rate. a second low level pulse on tbrl loads data into the transmitter buffer register (c). data transfer to the transmitter register is delayed until transmission of the cur- rent data is complete (d). data is automatically transferred to the transmitter register and transmission of that character begins one clock cycle later. receiver operation data is received in serial form at the receiver register input (rri). when no data is being received, rri must remain high. the data is clocked through the receiver register clock (rrc). the clock rate is 16 times the data rate. a low level on data received reset ( drr) clears the data receiver (dr) line (a). during the ?rst stop bit data is trans- ferred from the receiver register to the receiver buffer register (rbr) (b). if the word is less than 8 bits, the unused most signi?cant bits will be a logic low. the output character is right justi?ed to the least signi?cant bit rbr1. a logic high on overrun error (oe) indicates overruns. an overrun occurs when dr has not been cleared before the present character was transferred to the rbr. one clock cycle later dr is reset to a logic high, and framing error (fe) is evaluated (c). a logic high on fe indicates an invalid stop bit was received, a framing error. a logic high on parity error (pe) indicates a parity error. a b c d end of last stop bit 1/2 clock 0 to 1 clock data tbrl tbre tre tro 1 figure 1. transmitter timing (not to scale) figure 2. receiver timing (not to scale) a b c beginning of first stop bit 7 1/2 clock cycles 1 clock cycle rri rbr1-8, oe, pe drr dr fe figure 3. serial data format lsb msb ? start bit parity ? if enabled 1, 11/2 or 2 stop bits 5-8 data bits hd-6402
5-5 start bit detection the receiver uses a 16x clock timing. the start bit could have occurred as much as one clock cycle before it was detected, as indicated by the shaded portion (a). the center of the start bit is de?ned as clock count 7 1/2. if the receiver clock is a symmetrical square wave, the center of the start bit will be located within 1/2 clock cycle, 1/32 bit or 3.125% giving a receiver margin of 46.875%. the receiver begins searching for the next start bit at the center of the ?rst stop bit. interfacing with the hd-6402 clock rri input start 71/2 clock cycles 81/2 clock cycles count 71/2 defined center of start bit figure 4. a figure 5. typical serial data link digital system transmitter receiver rri tro tbr1 tbr8 control hd-6402 control rb1 rb8 digital system transmitter receiver rri tro tbr1 tbr8 control hd-6402 control rb1 rb8 rs232 driver rs232 receiver rs232 driver rs232 receiver hd-6402
5-6 absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0v input, output or i/o voltage applied. . . . . gnd -0.5v to v cc +0.5v storage temperature range . . . . . . . . . . . . . . . . . -65 o c to +150 o c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . +300 o c esd classi?cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 typical derating factor . . . . . . . . . . . . 1ma/mhz increase in iccop thermal resistance (typical) q ja q jc cerdip package . . . . . . . . . . . . . . . . 50 o c/w 12 o c/w pdip package . . . . . . . . . . . . . . . . . . . 50 o c/w n/a gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1643 gates caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. operating conditions operating voltage range . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v operating temperature range hd-6402r-9, hd6402b-9 . . . . . . . . . . . . . . . . . . .-40 o c to +85 o c dc electrical speci?cations v cc = 5.0v 10%, t a = -40 o c to +85 o c (hd-6402r-9, hd-6402b-9) symbol parameter limits units conditions min max v ih logical 1 input voltage 2.0 - v v cc = 5.5v v il logical 0 input voltage - 0.8 v v cc = 4.5v ii input leakage current -1.0 1.0 m av in = gnd or v cc , v cc = 5.5v v oh logical 1 output voltage 3.0 v cc -0.4 - - vi oh = -2.5ma, v cc = 4.5v i oh = -100 m a v ol logical 0 output voltage - 0.4 v i ol = +2.5ma, v cc = 4.5v i o output leakage current -1.0 1.0 m av o = gnd or v cc , v cc = 5.5v iccsb standby supply current - 100 m av in = gnd or v cc ; v cc = 5.5v, output open iccop operating supply current (see note) - 2.0 ma v cc = 5.5v, clock freq. = 2mhz, v in = v cc or gnd, outputs open note: guaranteed, but not 100% tested capacitance t a = +25 o c parameter symbol conditions limit units typical input capacitance cin freq. = 1mhz, all measurements are referenced to de- vice gnd 25 pf output capacitance cout 25 pf ac electrical speci?cations v cc = 5.0v 10%, t a = -40 o c to +85 o c (hd-6402r-9, hd6402b-9) symbol parameter limits hd-6402r limits hd-6402b units conditions min max min max (1) fclock clock frequency d.c. 2.0 d.c. 8.0 mhz c l = 50pf see switching waveform (2) t pw pulse widths, crl, drr, tbrl 150 - 75 - ns (3) t mr pulse width mr 150 - 150 - ns (4) t set input data setup time 50 - 20 - ns (5) t hold input data hold time 60 - 20 - ns (6) t en output enable time - 160 - 35 ns hd-6402
5-7 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?cations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com a.c. testing input, output waveform test circuit switching waveforms figure 6. data input cycle figure 7. control register load cycle figure 8. status flag output enable time or data out- put enable time tbr1 - tbr8 valid data tbrl (4) t set (2) t pw (5) t hold (5) t hold (2) t pw (4) t set valid data cls1, cls2, sbs, pi, epe crl (6) t en sfd rrd status or rbr1 - rbr8 figure 9. note: a.c. testing: all input signals must switch between v il - 50% v il and v ih + 20% v ih . input rise and fall times are driven at 1ns/v. input v ih + 20% v ih v il - 50% v il 1.5v 1.5v output v oh v ol figure 10. note: includes stray and jig capacitance, c l = 50pf. out c l (see note) hd-6402
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